An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VcM-based switching scheme. Moreover, the proposed method shows better linearity than the VcM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion- step. The measured peak DNL and 1NL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL 1 is observed at 4^-1 VFS and 4^-3 VFS, the same as the static nonlinearity model.
An ultra low voltage rectifier with high power conversion efficiency （PCE） for PE energy harvesting ap- plications is presented in this paper. This is achieved by utilizing the DTMOS which the body terminal is connected to the gate terminal in a diode connected transistor. This implementation facilitates the rectifier with dynamic con- trol over the threshold voltage. Moreover, we use input powered to take the place of output powered to reduce the power loss and thereby increasing the power conversion efficiency. Based on standard SMIC 0.18 μm CMOS tech- nology, the simulation results show that the voltage conversion efficiency and the power conversion efficiency can reach up to 90.5% and 95.5% respectively, when the input voltage equals to 0.2 V @ 100 Hz with load resistance 50 kW. Input voltages with frequencies in the range of 10 Hz-1 kHz can be rectified.
Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
The bufferless router emerges as an interesting option for cost-efficient in network-on-chip （NoC） de- sign. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router （LBBDR） for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle iden- tifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits con- tend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.
In a time-interleaved analog-to-digital converter （TI ADC）, several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying successive approximation register （SAR） converters as sub-channel ADCs. In spite of the advantages, this structure suffers from three mismatches, which are offset mismatch, gain mismatch, and time skew. This paper focuses on a TI SAR ADC with a number of channels. The mismatch effects in the frequency domain are analyzed and the derived close form formulas are verified based on Matlab. In addition, we clarify that the standard deviation of DNL and INL of an M-channel TI ADC is reduced by a factor of ~ compared to a single channel ADC. The formulas can be used to derive the corresponding requirements when designing a TI ADC. Our analysis process is able to inform the study of calibration algorithms.
A high efficiency, high power factor, and linear constant current LED driver based on adaptive seg- mented linear architecture is presented. When the input voltage varied, the proposed LED driver automatically switched over LED strings according to the segmented LED voltage drop, which increased the LED lighting time. The efficiency and power factor are improved, while the system design is simplified by this control scheme. Without the usage of electrolytic capacitor and magnetic components, the proposed driver possesses advantages of smaller size, longer lifetime and lower cost over others. The proposed driver is implemented in 0.8 μm 5 V/40 V HVCMOS process, which occupies an active area of 820× 920μm2. The measured results show that the average value of the internal reference voltage is 500 4- 7 mV, with a standard deviation of only 4.629 mV, thus LED current can be set accurately. Under 220 V root mean square 50 Hz utility voltage and the number ratio of the three LED strings being 47 ： 17 ： 16, the system can realize a high power factor of 0.974 and power conversion efficiency of 93.4%.
A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.
A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC.The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy.The SAR-based and ＂half-gain＂ MDAC reduce the power consumption and core area.The dynamic comparator and SAR control logic are applied to reduce power consumption.Implemented in 180 nm CMOS,the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.
